The inventive concept relates to an image sensor, such as a complementary metal-oxide semiconductor (CMOS) image sensor, having a stacked structure in which two semiconductor chips are bonded to each other.
Generally, a CMOS image sensor (CIS) may include a pixel area and a logic area. In the pixel area, a plurality of pixels are arranged in a two-dimensional array structure, wherein each pixel includes a photodiode and several pixel transistors. The pixel transistors may include, for example, a transfer transistor, a reset transistor, a source follower transistor, and a selecting transistor. Logic circuits for processing pixel signals from the pixel area may be arranged in the logic area. Recently, a CIS has been developed where a pixel area is formed on one chip and a logic area is formed on another chip and the two chips are stacked together. A CIS having such a stacked structure may provide images with high image quality due to, for example, being able to increase of the number of pixels in the pixel area without decreasing their size and/or optimization of performance of logic circuits in the logic area.